
Event-triggered Implicit Perturbation for Zeroth-Order Fine-Tuning of Spiking Transformers
Replaces explicit read-modify-write weight perturbation with perturbation sums from dedicated hardware attached to an IMC array for zeroth-order fine-tuning of spiking networks. Compared with the simplified variant, it requires 40%-46% more silicon area and 15%-49% more energy per operation, plus custom 16 nm CMOS fabrication or synthesis. It is a circuit for SNNs, rather than software deployable on a 24 GB GPU or through a third-party API.








































