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abstract indexed · arXiv 2609.16367 · updated 2026-10-18

FINNAS: FINN-Guided Hardware-Aware NAS and Pruning for FPGA Jet Substructure Classification

First page of FINNAS: FINN-Guided Hardware-Aware NAS and Pruning for FPGA Jet Substructure Classification
From the original paper · arXiv 2609.16367Page 1. Select the image to read the PDF.

The method replaces manual design-space exploration of quantised MLP accelerators for FPGAs with an evolutionary NAS that jointly searches depth, width, and precision, ranking candidates with FINN-estimated LUT and latency proxies before pruning and RTL validation. It costs access to the FINN/Vivado FPGA toolchain, repeated synthesis-in-the-loop evaluation during search, and acceptance of fully parallel mappings whose proxy estimates must be confirmed by out-of-context synthesis. It can fail when the search proxies mispredict post-synthesis resource or latency figures, when results do not transfer off the specific jet-substructure task and target FPGA, and it is irrelevant to deployments on GPU or API-served models.

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recommendation
watch
research area
efficient architectures
technical change
Hardware-aware evolutionary NAS for FPGA QNNs
published
2026-09-14

The technique targets FPGA accelerator design, which the reader's single-GPU/API infrastructure does not involve, so it is only worth tracking in case future edge-hardware deployment becomes a requirement.

Central equations

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The estimated accuracy and hardware metrics are combined through the reward R⁡(x) defined in Equation 2.

R⁡(x)=A⁡(x)⋅max⁡(1,L⁡(x)Bl)−βl⋅max⁡(1,T⁡(x)Bt)−βt

equation (2) · §II Methodology and Design · proposed method

Each individual is encoded as Equation 1, i.e., an ordered list of hidden-layer widths and four global precision fields. At initialisation, L, every hi, and each precision field are drawn from their corresponding finite sets in Table I. Samples are repaired until they satisfy Bo​a≥Bh​a and Bw<8 when all activation precisions are below 8 bits. Each candidate then undergoes 16 epochs of proxy training using cross-entropy loss and the AdamW optimiser to obtain validation accuracy A⁡(x).

x={[h1,…,hL],(Bw,Bi​a,Bh​a,Bo​a)}

equation (1) · §II Methodology and Design · proposed method

equations from arXiv HTML · fetched 2026-10-13

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  1. claim 01Paperraft inference
    Read the brief interpretation

    The method replaces manual design-space exploration of quantised MLP accelerators for FPGAs with an evolutionary NAS that jointly searches depth, width, and precision, ranking candidates with FINN-estimated LUT and latency proxies before pruning and RTL validation. It costs access to the FINN/Vivado FPGA toolchain, repeated synthesis-in-the-loop evaluation during search, and acceptance of fully parallel mappings whose proxy estimates must be confirmed by out-of-context synthesis. It can fail when the search proxies mispredict post-synthesis resource or latency figures, when results do not transfer off the specific jet-substructure task and target FPGA, and it is irrelevant to deployments on GPU or API-served models.

    This is a Paperraft inference. It is not pinned to a verified PDF passage.

    Inspect the source
  2. claim 02Paperraft inference

    A searched compact design improves accuracy from 73.78% to 74.36% while reducing LUT usage by 8.5x and RTL-simulation latency by 1.77x versus a manually optimised dense FINN accelerator; unstructured pruning adds further LUT and FF reductions.

    This is a Paperraft inference. It is not pinned to a verified PDF passage.

    Inspect the source

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