MeshKV: A Network-on-Chip KV Cache Fabric for Scalable Transformer Decoding Accelerators

Long customer conversations exhaust memory or limit concurrent requests.

What you would change

Change only the attention cache policy, after checking model and runtime support.

Change only the attention cache policy, after checking model and runtime support.

Compare against

The same model with its ordinary attention cache.

1. Locate the paper's implementation and check its license, model support, data needs, and hardware requirements. Stop here if you cannot obtain the required artifacts.
2. Save a small set of representative product tasks and expected outcomes. Keep evaluation tasks out of any training or tuning, and choose quality and cost limits before running.
3. Run the baseline and the proposed change on identical inputs. Keep other settings fixed and repeat paired runs to expose variation.
4. Save per-task outputs, failures, timings, and all usage costs. Review regressions before expanding the test.

What to measure

Peak cache memory, long-context answer quality, first-token latency, and requests completed.

When to keep it

Keep the change only if it meets your preselected quality and latency limits and improves the metric you care about after setup and operating costs. Otherwise retain the baseline. This is an exploration plan, not a validated recommendation.

recommendation

watch

research area

KV cache

technical change

NoC packetized KV cache fabric for tiled accelerators

published

2026-09-16

The technique is demonstrated only on a custom 8x8 FPGA NoC prototype, so its throughput claims are credible but not actionable for a reader limited to one 24 GB GPU or managed APIs.

1. claim 01Paperraft inference
   Read the brief interpretation

   It replaces compression and DRAM-placement KV systems that concentrate traffic on centralized memory paths with a packetized KV fabric over a lightweight NoC, using affine striping, multicast with duplicate suppression, and prefetch/softmax overlap behind credit-aligned FIFOs. The cost is a custom tiled FPGA/accelerator design with NoC routing, credit-aligned buffering, and verified duplicate suppression, which is substantial hardware complexity and not portable to a commodity 24 GB GPU or third-party API. It can fail to transfer because the reported gains are specific to an 8x8 FPGA prototype under multi-stream long-context load, depend on NoC topology and flow control correctness, and do not address the DRAM/HBM and kernel bottlenecks that dominate single-GPU serving.

   This is a Paperraft inference. It is not pinned to a verified PDF passage.

   Inspect the source
2. claim 02Paperraft inference

   On an 8x8 FPGA with LLaMA-2-7B and Mistral-7B at 8K-32K context, MeshKV reports up to 1.9x multi-stream throughput, 2.1x KV bandwidth utilization, and up to 58% lower interconnect traffic.

   This is a Paperraft inference. It is not pinned to a verified PDF passage.

   Inspect the source