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  "builder_plan": {
    "scenario": "A self-hosted assistant is too expensive because its model uses most of the GPU memory.",
    "change": "Try the paper's supported lower-precision weights on a copy of your serving setup.",
    "baseline": "The same model at its original precision, on the same GPU.",
    "steps": [
      "Locate the paper's implementation and check its license, model support, data needs, and hardware requirements. Stop here if you cannot obtain the required artifacts.",
      "Save a small set of representative product tasks and expected outcomes. Keep evaluation tasks out of any training or tuning, and choose quality and cost limits before running.",
      "Run the baseline and the proposed change on identical inputs. Keep other settings fixed and repeat paired runs to expose variation.",
      "Save per-task outputs, failures, timings, and all usage costs. Review regressions before expanding the test."
    ],
    "measure": "Peak memory, task pass rate, latency, and total serving cost at the same context and load.",
    "decision": "Keep the change only if it meets your preselected quality and latency limits and improves the metric you care about after setup and operating costs. Otherwise retain the baseline. This is an exploration plan, not a validated recommendation."
  },
  "builder_review": null,
  "arxiv_id": "2610.26083",
  "title": "MX-Like Tensor Core for LLM Inference with NPU Integration via Hardware-Software Co-Design Exploration",
  "summary": "The work does not replace a software technique; it replaces ad hoc selection of block-scaled quantization formats (OCP MX, NVFP4) with a systematic HW-SW co-design exploration of scale, weight, and activation format combinations on a specialized NPU MAC datapath. For a software practitioner the actionable finding is narrow: scale format choice matters mainly under aggressive FP4 quantization, where UE5M3 scales improve accuracy at negligible silicon cost. Adoption fails at the reader's constraints because the gains are realized only in custom NPU silicon (SNAX platform), cannot be enabled on a commodity 24 GB GPU or third-party API, and the perplexity results may not transfer across models or calibration pipelines.",
  "rationale": "The contribution is a hardware co-design guideline for NPU-based edge deployment, which the reader cannot implement on a single GPU or via APIs, though the UE5M3 finding is worth monitoring if FP4 inference hardware or kernels become accessible.",
  "technique": "MX-like block-scaled quantization format exploration with NPU co-design",
  "family": "quantizacao",
  "recommendation": "observar",
  "published": "2026-10-19",
  "as_of": "2026-10-20",
  "editorial_status": "indexed",
  "source_url": "https://arxiv.org/abs/2610.26083",
  "independent_implementations": 0,
  "total_implementations": 1,
  "stars": 0,
  "citations": null,
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