{
  "schema_version": 1,
  "builder_plan": {
    "scenario": "Your inference service slows down when several customers send requests together.",
    "change": "Replay a recorded request trace with only the proposed serving policy changed.",
    "baseline": "Your current scheduler on the same model and hardware.",
    "steps": [
      "Locate the paper's implementation and check its license, model support, data needs, and hardware requirements. Stop here if you cannot obtain the required artifacts.",
      "Save a small set of representative product tasks and expected outcomes. Keep evaluation tasks out of any training or tuning, and choose quality and cost limits before running.",
      "Run the baseline and the proposed change on identical inputs. Keep other settings fixed and repeat paired runs to expose variation.",
      "Save per-task outputs, failures, timings, and all usage costs. Review regressions before expanding the test."
    ],
    "measure": "Requests meeting your latency target, throughput, failures, and cost per successful request.",
    "decision": "Keep the change only if it meets your preselected quality and latency limits and improves the metric you care about after setup and operating costs. Otherwise retain the baseline. This is an exploration plan, not a validated recommendation."
  },
  "builder_review": null,
  "arxiv_id": "2610.23503",
  "title": "HBFSim: A Simulator for Exploring HBF in Memory Hierarchies for LLMs",
  "summary": "HBFSim is an event-driven simulator that replaces guesswork or ad-hoc profiling when evaluating hypothetical HBM+HBF memory hierarchies for LLM decoding; it does not replace any production component, since HBF hardware is not yet commercially available. It costs engineering time to configure and calibrate against a serving frontend, and its results are only as reliable as the assumed, unpublished HBF device parameters. Conclusions drawn today can fail because real HBF latency, bandwidth, and endurance characteristics may diverge from the modeled values, and the finding that HBM should hold running KV cache rather than cache HBF may not transfer to other workloads or devices.",
  "rationale": "The paper explores a hardware technology (High Bandwidth Flash) that does not yet exist as a purchasable device, so the reader with a single 24 GB GPU cannot adopt anything; the only actionable takeaway is to monitor HBF as a future capacity tier and note the simulator's design guidance on HBM usage.",
  "technique": "Simulator for HBM+HBF heterogeneous memory hierarchies",
  "family": "serving_e_batching",
  "recommendation": "observar",
  "published": "2026-10-16",
  "as_of": "2026-10-19",
  "editorial_status": "indexed",
  "source_url": "https://arxiv.org/abs/2610.23503",
  "independent_implementations": 0,
  "total_implementations": 0,
  "stars": 0,
  "citations": null,
  "claims": [
    {
      "claim_id": "claim-01",
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      "claim_id": "claim-02",
      "statement": "HBF serves data that does not fit in HBM 11.0-19.0x faster than host DRAM; at published peak load of Llama-3.1-70B, HBF endurance is 2.0 to 6.9 years depending on the number of stacks sharing KV writes.",
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  "validation_tier": "unknown",
  "evidence_tier": "unknown",
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