{
  "schema_version": 1,
  "builder_plan": {
    "scenario": "You already need task-specific training and want to reduce its memory or compute cost.",
    "change": "Change only the training technique on a small controlled run after checking prerequisites.",
    "baseline": "Your current training recipe with the same model, data split, and evaluation.",
    "steps": [
      "Locate the paper's implementation and check its license, model support, data needs, and hardware requirements. Stop here if you cannot obtain the required artifacts.",
      "Save a small set of representative product tasks and expected outcomes. Keep evaluation tasks out of any training or tuning, and choose quality and cost limits before running.",
      "Run the baseline and the proposed change on identical inputs. Keep other settings fixed and repeat paired runs to expose variation.",
      "Save per-task outputs, failures, timings, and all usage costs. Review regressions before expanding the test."
    ],
    "measure": "Held-out quality, peak memory, training time, and full compute cost to the target quality.",
    "decision": "Keep the change only if it meets your preselected quality and latency limits and improves the metric you care about after setup and operating costs. Otherwise retain the baseline. This is an exploration plan, not a validated recommendation."
  },
  "builder_review": null,
  "arxiv_id": "2610.12444",
  "title": "Rounding in Preconditioner Space: Redesigning 4-bit AdamW Optimizer-State Quantization",
  "summary": "Replaces standard 4-bit AdamW optimizer-state quantization (e.g., TorchAO) with zero-inclusive preconditioner-space stochastic rounding or zero-excluding EDEN-calibrated NF4 codebooks for the second moment, plus targeted stochastic rounding of the LM-head first moment in the final 10% of training. Cost is a modified optimizer implementation, slight extra compute for per-block stochastic rounding and rescaling, and some residual quality gap relative to 32-bit AdamW; memory saved versus full-precision states is substantial but the two moments still require storage. Failure modes include quality degradation if the second-moment codebook mishandles near-zero values (the distortion the paper analyzes), reliance on implementation details such as block size and rounding schedule, and validation only at pretraining scales up to 2.7B, so behavior on larger or different workloads is unverified.",
  "rationale": "On a single 24 GB GPU, 4-bit optimizer states directly expand the trainable model size or batch size, and the method is a drop-in optimizer change, but the quality benefit over existing 4-bit baselines is workload-dependent and requires a custom or patched optimizer, so it warrants a small-scale validation run before production adoption.",
  "technique": "Preconditioner-space stochastic rounding for 4-bit AdamW states",
  "family": "treino_eficiente",
  "recommendation": "testar",
  "published": "2026-10-08",
  "as_of": "2026-10-18",
  "editorial_status": "indexed",
  "source_url": "https://arxiv.org/abs/2610.12444",
  "independent_implementations": 0,
  "total_implementations": 1,
  "stars": 1,
  "citations": null,
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      "statement": "Both ZIP-SR and ZE-EDEN reduce TorchAO 4-bit AdamW's mean validation-loss gap to 32-bit AdamW at every evaluated size (130M-2.7B), with the largest reported gap reduction reaching 70%; 4-bit states imply roughly 8x compression of each optimizer state versus 32-bit, though the abstract does not state this as a factor.",
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  "report_available": false,
  "validation_tier": "unknown",
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  "equations_status": "not_fetched",
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}