{
  "schema_version": 1,
  "builder_plan": {
    "scenario": "Start with one repeated product task that has a measurable failure or cost.",
    "change": "Read the methods and identify one change you can isolate in that workflow.",
    "baseline": "Your current implementation on the same held-out tasks.",
    "steps": [
      "Locate the paper's implementation and check its license, model support, data needs, and hardware requirements. Stop here if you cannot obtain the required artifacts.",
      "Save a small set of representative product tasks and expected outcomes. Keep evaluation tasks out of any training or tuning, and choose quality and cost limits before running.",
      "Run the baseline and the proposed change on identical inputs. Keep other settings fixed and repeat paired runs to expose variation.",
      "Save per-task outputs, failures, timings, and all usage costs. Review regressions before expanding the test."
    ],
    "measure": "Successful outcomes, response time, human rework, and total cost per successful task.",
    "decision": "Keep the change only if it meets your preselected quality and latency limits and improves the metric you care about after setup and operating costs. Otherwise retain the baseline. This is an exploration plan, not a validated recommendation."
  },
  "builder_review": null,
  "arxiv_id": "2610.10403",
  "title": "SUSpMV: A High Frequency Sparse Matrix Vector Multiplier on HBM Enabled FPGA written in SUS",
  "summary": "The technique replaces prior FPGA SpMV accelerators with a deeply pipelined design written in the SUS HDL, using all 32 HBM channels for matrix streaming and DDR for vectors. It costs specialized FPGA hardware (Alveo U280), a custom matrix storage format, and development in an upcoming, immature HDL toolchain. Adoption can fail when matrix sparsity patterns do not suit the dual density-adaptive format, and performance depends on sustaining HBM bandwidth across irregular memory access.",
  "rationale": "This is FPGA hardware design for sparse linear algebra kernels, not a technique applicable to LLM inference or training on a single 24 GB GPU or third-party APIs, so it falls outside the reader's production practice.",
  "technique": "Deep-pipelined SpMV accelerator on HBM FPGA",
  "family": "outro",
  "recommendation": "nao_aplica",
  "published": "2026-10-07",
  "as_of": "2026-10-18",
  "editorial_status": "indexed",
  "source_url": "https://arxiv.org/abs/2610.10403",
  "independent_implementations": 0,
  "total_implementations": 0,
  "stars": 0,
  "citations": null,
  "claims": [
    {
      "claim_id": "claim-01",
      "statement": "The technique replaces prior FPGA SpMV accelerators with a deeply pipelined design written in the SUS HDL, using all 32 HBM channels for matrix streaming and DDR for vectors. It costs specialized FPGA hardware (Alveo U280), a custom matrix storage format, and development in an upcoming, immature HDL toolchain. Adoption can fail when matrix sparsity patterns do not suit the dual density-adaptive format, and performance depends on sustaining HBM bandwidth across irregular memory access.",
      "basis": "inferred",
      "result": "",
      "baseline": "",
      "conditions": "",
      "source_url": "https://arxiv.org/abs/2610.10403",
      "source_page": null,
      "source_excerpt": ""
    },
    {
      "claim_id": "claim-02",
      "statement": "79% geometric mean throughput improvement over prior work on the same Alveo U280 platform, with peak throughput of 144.9 GFLOPs (94% of theoretical peak) versus 98 GFLOPs for prior work.",
      "basis": "inferred",
      "result": "",
      "baseline": "",
      "conditions": "",
      "source_url": "https://arxiv.org/abs/2610.10403",
      "source_page": null,
      "source_excerpt": ""
    }
  ],
  "exposure_map": [
    {
      "dimension": "quality",
      "basis": "not_evaluated",
      "finding": "",
      "interpretation": "",
      "limitation": "",
      "next_check": "",
      "source_url": "",
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    },
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      "dimension": "compute",
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      "source_url": "",
      "source_page": null,
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    },
    {
      "dimension": "latency",
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      "source_page": null,
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    },
    {
      "dimension": "operations",
      "basis": "not_evaluated",
      "finding": "",
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      "limitation": "",
      "next_check": "",
      "source_url": "",
      "source_page": null,
      "source_excerpt": ""
    },
    {
      "dimension": "compatibility",
      "basis": "not_evaluated",
      "finding": "",
      "interpretation": "",
      "limitation": "",
      "next_check": "",
      "source_url": "",
      "source_page": null,
      "source_excerpt": ""
    },
    {
      "dimension": "security",
      "basis": "not_evaluated",
      "finding": "",
      "interpretation": "",
      "limitation": "",
      "next_check": "",
      "source_url": "",
      "source_page": null,
      "source_excerpt": ""
    },
    {
      "dimension": "data_and_training",
      "basis": "not_evaluated",
      "finding": "",
      "interpretation": "",
      "limitation": "",
      "next_check": "",
      "source_url": "",
      "source_page": null,
      "source_excerpt": ""
    },
    {
      "dimension": "reproducibility",
      "basis": "not_evaluated",
      "finding": "",
      "interpretation": "",
      "limitation": "",
      "next_check": "",
      "source_url": "",
      "source_page": null,
      "source_excerpt": ""
    }
  ],
  "risks": [],
  "minimum_test": [],
  "open_questions": [],
  "independent_tests": [],
  "lab_reproductions": [],
  "report_available": false,
  "validation_tier": "unknown",
  "evidence_tier": "unknown",
  "infrastructure_basis": "unknown",
  "equations": [],
  "equations_status": "not_fetched",
  "core_kind": "",
  "equations_fetched_at": "",
  "equations_source_url": "",
  "equations_source_sha256": "",
  "exposures_reviewed_at": "",
  "exposures_source_sha256": ""
}