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abstract indexed · arXiv 2609.29727 · updated 2026-10-18

VQ-LIC: Shared Vector-Quantized Learned Image Compression on a Resource-Constrained FPGA

First page of VQ-LIC: Shared Vector-Quantized Learned Image Compression on a Resource-Constrained FPGA
From the original paper · arXiv 2609.29727Page 1. Select the image to read the PDF.

VQ-LIC replaces a conventional learned image compression encoder and separate VQ compute array with an asymmetric edge-cloud codec: a compact INT8 depthwise-pointwise analysis transform plus multi-codebook VQ on the FPGA edge, sharing one reusable DW/PW engine pair, with reconstruction offloaded to a large cloud decoder. The cost is infrastructure mismatch for this reader: it requires FPGA deployment with custom RTL, an edge-cloud split architecture, and accepts a modest PSNR tradeoff (28.69 dB at 0.1398 bpp) relative to larger codecs. It can fail if the target deployment lacks an FPGA edge device or a cloud decoder endpoint, if the RTL latency model does not transfer to other silicon, and if the PSNR degradation is unacceptable for the application's quality requirements.

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technical change
FPGA vector-quantized learned image codec
published
2026-09-24

The technique is an FPGA hardware codec for image compression, which is outside the reader's GPU/API-based ML production scope and offers no adoptable component for their stack.

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    VQ-LIC replaces a conventional learned image compression encoder and separate VQ compute array with an asymmetric edge-cloud codec: a compact INT8 depthwise-pointwise analysis transform plus multi-codebook VQ on the FPGA edge, sharing one reusable DW/PW engine pair, with reconstruction offloaded to a large cloud decoder. The cost is infrastructure mismatch for this reader: it requires FPGA deployment with custom RTL, an edge-cloud split architecture, and accepts a modest PSNR tradeoff (28.69 dB at 0.1398 bpp) relative to larger codecs. It can fail if the target deployment lacks an FPGA edge device or a cloud decoder endpoint, if the RTL latency model does not transfer to other silicon, and if the PSNR degradation is unacceptable for the application's quality requirements.

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  2. claim 02Paperraft inference

    Uses an order of magnitude fewer DSPs than comparable FPGA LIC accelerators; post-training codebook reduction cuts VQ arithmetic and codebook storage by 4x; full pipeline runs at 47.98 fps and 42.84 mJ per frame on a Zynq-7020.

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