{
  "schema_version": 1,
  "builder_plan": {
    "scenario": "A support or data assistant repeats work across related customer requests.",
    "change": "Try the paper's memory change in a replay of past tasks, with separate memory per customer.",
    "baseline": "Your current memory pipeline plus a no-memory control using the same agent.",
    "steps": [
      "Locate the paper's implementation and check its license, model support, data needs, and hardware requirements. Stop here if you cannot obtain the required artifacts.",
      "Save a small set of representative product tasks and expected outcomes. Keep evaluation tasks out of any training or tuning, and choose quality and cost limits before running.",
      "Run the baseline and the proposed change on identical inputs. Keep other settings fixed and repeat paired runs to expose variation.",
      "Save per-task outputs, failures, timings, and all usage costs. Review regressions before expanding the test."
    ],
    "measure": "Task success, stale memories, retrieval misses, response latency, and all memory maintenance costs.",
    "decision": "Keep the change only if it meets your preselected quality and latency limits and improves the metric you care about after setup and operating costs. Otherwise retain the baseline. This is an exploration plan, not a validated recommendation."
  },
  "builder_review": null,
  "arxiv_id": "2609.18675",
  "title": "HBFlex: A Flexible Memory System for Bridging Fine-Grained LLM States and Coarse-Grained HBF Parallel Execution",
  "summary": "HBFlex replaces hybrid HBM/HBF KV-cache placement (and baselines such as FlashAccel and H3) with a full-HBF design that balances KV placement across flash planes, batches incremental writes into compute windows, and defers garbage collection using lifetime-guided block packing. The cost is dependence on HBF hardware that is not commercially available to the reader, plus substantial systems complexity in placement, writeback scheduling, and reclamation logic, with results demonstrated only in trace-driven simulation rather than on a deployed serving stack. It can fail if real workload traces diverge from simulated ones, if write-read interference is underestimated under bursty decode traffic, or if HBF endurance and garbage-collection overheads prove worse in production silicon.",
  "rationale": "The technique requires HBF hardware and a custom memory system that the reader cannot procure or deploy on a 24 GB GPU or API-based setup, and its gains are simulation-only, so it is worth tracking but not actionable.",
  "technique": "Full-HBF KV-cache memory system for LLM serving",
  "family": "memoria_e_contexto",
  "recommendation": "observar",
  "published": "2026-09-16",
  "as_of": "2026-10-18",
  "editorial_status": "indexed",
  "source_url": "https://arxiv.org/abs/2609.18675",
  "independent_implementations": 0,
  "total_implementations": 1,
  "stars": 1,
  "citations": 0,
  "claims": [
    {
      "claim_id": "claim-01",
      "statement": "HBFlex replaces hybrid HBM/HBF KV-cache placement (and baselines such as FlashAccel and H3) with a full-HBF design that balances KV placement across flash planes, batches incremental writes into compute windows, and defers garbage collection using lifetime-guided block packing. The cost is dependence on HBF hardware that is not commercially available to the reader, plus substantial systems complexity in placement, writeback scheduling, and reclamation logic, with results demonstrated only in trace-driven simulation rather than on a deployed serving stack. It can fail if real workload traces diverge from simulated ones, if write-read interference is underestimated under bursty decode traffic, or if HBF endurance and garbage-collection overheads prove worse in production silicon.",
      "basis": "inferred",
      "result": "",
      "baseline": "",
      "conditions": "",
      "source_url": "https://arxiv.org/abs/2609.18675",
      "source_page": null,
      "source_excerpt": ""
    },
    {
      "claim_id": "claim-02",
      "statement": "Trace-driven simulation reports average throughput speedups of up to 1.58x over FlashAccel and 3.30x over H3 by serving KV cache entirely from High-Bandwidth Flash with coordinated read balancing, write scheduling, and deferred reclamation.",
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      "result": "",
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      "source_url": "https://arxiv.org/abs/2609.18675",
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      "source_excerpt": ""
    }
  ],
  "exposure_map": [
    {
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      "finding": "",
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      "next_check": "",
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    },
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      "dimension": "compute",
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    },
    {
      "dimension": "latency",
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      "finding": "",
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      "source_page": null,
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    },
    {
      "dimension": "operations",
      "basis": "not_evaluated",
      "finding": "",
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      "source_page": null,
      "source_excerpt": ""
    },
    {
      "dimension": "compatibility",
      "basis": "not_evaluated",
      "finding": "",
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      "next_check": "",
      "source_url": "",
      "source_page": null,
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    },
    {
      "dimension": "security",
      "basis": "not_evaluated",
      "finding": "",
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      "source_page": null,
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    },
    {
      "dimension": "data_and_training",
      "basis": "not_evaluated",
      "finding": "",
      "interpretation": "",
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      "next_check": "",
      "source_url": "",
      "source_page": null,
      "source_excerpt": ""
    },
    {
      "dimension": "reproducibility",
      "basis": "not_evaluated",
      "finding": "",
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      "next_check": "",
      "source_url": "",
      "source_page": null,
      "source_excerpt": ""
    }
  ],
  "risks": [],
  "minimum_test": [],
  "open_questions": [],
  "independent_tests": [],
  "lab_reproductions": [],
  "report_available": false,
  "validation_tier": "unknown",
  "evidence_tier": "unknown",
  "infrastructure_basis": "unknown",
  "equations": [],
  "equations_status": "not_fetched",
  "core_kind": "",
  "equations_fetched_at": "",
  "equations_source_url": "",
  "equations_source_sha256": "",
  "exposures_reviewed_at": "",
  "exposures_source_sha256": ""
}