{ "schema_version": 1, "builder_plan": { "scenario": "Start with one repeated product task that has a measurable failure or cost.", "change": "Read the methods and identify one change you can isolate in that workflow.", "baseline": "Your current implementation on the same held-out tasks.", "steps": [ "Locate the paper's implementation and check its license, model support, data needs, and hardware requirements. Stop here if you cannot obtain the required artifacts.", "Save a small set of representative product tasks and expected outcomes. Keep evaluation tasks out of any training or tuning, and choose quality and cost limits before running.", "Run the baseline and the proposed change on identical inputs. Keep other settings fixed and repeat paired runs to expose variation.", "Save per-task outputs, failures, timings, and all usage costs. Review regressions before expanding the test." ], "measure": "Successful outcomes, response time, human rework, and total cost per successful task.", "decision": "Keep the change only if it meets your preselected quality and latency limits and improves the metric you care about after setup and operating costs. Otherwise retain the baseline. This is an exploration plan, not a validated recommendation." }, "builder_review": null, "arxiv_id": "2609.17057", "title": "Budgeted Express-Mesh: Traffic-Aware Link Placement and Deadlock-Free Adaptive Routing", "summary": "This is a network-on-chip topology-routing co-design that replaces a standard mesh interconnect with a mesh augmented by a few traffic-aware express links placed under a fixed wire budget, using greedy placement refined by simulated annealing and committed top-K adaptive routing. It costs wire-budget allocation, placement optimization compute, and routing logic complexity, all at chip-design level. It can fail when traffic patterns deviate from those used to guide link placement, and it is entirely irrelevant to ML inference or training on a single 24 GB GPU or API-based stack.", "rationale": "The technique targets hardware NoC design, not any layer of the ML software or serving stack the reader operates.", "technique": "Traffic-aware express-link placement with adaptive NoC routing", "family": "outro", "recommendation": "nao_aplica", "published": "2026-09-15", "as_of": "2026-10-18", "editorial_status": "indexed", "source_url": "https://arxiv.org/abs/2609.17057", "independent_implementations": 0, "total_implementations": 0, "stars": 0, "citations": 0, "claims": [ { "claim_id": "claim-01", "statement": "This is a network-on-chip topology-routing co-design that replaces a standard mesh interconnect with a mesh augmented by a few traffic-aware express links placed under a fixed wire budget, using greedy placement refined by simulated annealing and committed top-K adaptive routing. It costs wire-budget allocation, placement optimization compute, and routing logic complexity, all at chip-design level. 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