{
  "schema_version": 1,
  "builder_plan": {
    "scenario": "A self-hosted model uses more compute or memory than your workload can justify.",
    "change": "Check for a usable pruned checkpoint and runtime support before attempting model surgery.",
    "baseline": "The original unpruned model at the same precision, context, and load.",
    "steps": [
      "Locate the paper's implementation and check its license, model support, data needs, and hardware requirements. Stop here if you cannot obtain the required artifacts.",
      "Save a small set of representative product tasks and expected outcomes. Keep evaluation tasks out of any training or tuning, and choose quality and cost limits before running.",
      "Run the baseline and the proposed change on identical inputs. Keep other settings fixed and repeat paired runs to expose variation.",
      "Save per-task outputs, failures, timings, and all usage costs. Review regressions before expanding the test."
    ],
    "measure": "Task quality, actual GPU memory, serving throughput, and preparation cost.",
    "decision": "Keep the change only if it meets your preselected quality and latency limits and improves the metric you care about after setup and operating costs. Otherwise retain the baseline. This is an exploration plan, not a validated recommendation."
  },
  "builder_review": null,
  "arxiv_id": "2609.05081",
  "title": "Deep Microcompression: Structured Pruning and Bit-packed Quantization for Microcontrollers",
  "summary": "DMC replaces runtime interpreter-based inference frameworks (e.g., TensorFlow Lite) on microcontrollers with a compile-time pipeline combining structured pruning, quantization-aware training, and fixed-length bit-packing that emits a dependency-free C library. The cost is a full retraining cycle with quantization-aware training, architecture-specific pruning decisions, and demonstrated results limited to a small CNN (LeNet-5) rather than modern model families. It can fail when target workloads require larger models whose accuracy does not survive aggressive pruning and bit-packed quantization, or when the hand-generated C path must be revalidated for each new chip or model revision.",
  "rationale": "The reader's production work targets GPU- or API-hosted models, so bare-metal MCU deployment is outside their infrastructure, making this relevant only if edge deployment on constrained hardware becomes a requirement.",
  "technique": "Structured pruning with bit-packed quantization for MCU inference",
  "family": "esparsidade_e_poda",
  "recommendation": "observar",
  "published": "2026-09-04",
  "as_of": "2026-10-18",
  "editorial_status": "indexed",
  "source_url": "https://arxiv.org/abs/2609.05081",
  "independent_implementations": 0,
  "total_implementations": 0,
  "stars": 0,
  "citations": 0,
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    {
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      "statement": "55.8x weight compression on LeNet-5 at 98.77% accuracy; 3x smaller binary than TensorFlow Lite on RP2040; first documented CNN deployment on ATmega328P (2KB SRAM)",
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    },
    {
      "dimension": "compatibility",
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    {
      "dimension": "security",
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    {
      "dimension": "data_and_training",
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  ],
  "risks": [],
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  "lab_reproductions": [],
  "report_available": false,
  "validation_tier": "unknown",
  "evidence_tier": "unknown",
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  "equations_status": "no_equations",
  "core_kind": "",
  "equations_fetched_at": "2026-09-26",
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}